In semiconductor memory devices, data is read from or written to the memory using address signals and various other control signals. In random access memories (“RAMs”), an individual binary data state (e.g., a bit) is stored in a volatile memory cell, wherein a number of such cells are grouped together into arrays of columns and rows accessible in random fashion along bitlines and wordlines, respectively, wherein each cell is associated with a unique wordline and bitline pair. Address decoder control circuits identify one or more cells to be accessed in a particular memory operation for reading or writing, wherein the memory cells are typically accessed in groups of bytes or words (e.g., generally a multiple of 8 cells arranged along a common wordline). Thus, by specifying an address, a RAM is able to access a single byte or word in an array of many cells, so as to read or write data from or into that addressed memory cell group.
Two major classes of random access memories include “dynamic” (e.g., DRAMs) and “static” (e.g., SRAMs) devices, both of which do not maintain the stored data when power is removed. For a DRAM device, data is stored in a capacitor, where an access transistor gated by a wordline selectively couples the capacitor to a bit line. DRAMs are relatively simple, and typically occupy less area than SRAMs. However, DRAMs require periodic refreshing of the stored data, because the charge stored in the cell capacitors tends to dissipate. Accordingly DRAMs need to be refreshed periodically in order to preserve the content of the memory. SRAM devices, on the other hand, do not need to be refreshed. SRAM cells typically include several transistors configured as a latch or flip-flop having two stable states, representative of two binary data states. Since the SRAM cells include several transistors, however, SRAM cells occupy more area than do DRAM cells. However, SRAM cells operate relatively quickly and do not require refreshing and the associated logic circuitry for refresh operations.
A major disadvantage of SRAM and DRAM devices is volatility, wherein removing power from such devices causes the data stored therein to be lost. For instance, the charge stored in DRAM cell capacitors dissipates after power has been removed, and the voltage used to preserve the latch data states in SRAM cells drops to zero, by which the latch loses its data. Accordingly, SRAMs and DRAMs are commonly referred to as “volatile” memory devices. Non-volatile memories are available, such as Flash and EEPROM. However, these types of non-volatile memory have operational limitations on the number of write cycles.
Another form of non-volatile memory is ferroelectric RAM devices, sometimes referred to as FERAMs or FRAMs. FERAM cells employ ferroelectric cell capacitors including a ferroelectric material between a pair of capacitor plates. Ferroelectric materials have two different stable polarization states that may be used to store binary information, where the ferroelectric behavior follows a hysteresis curve of polarization versus applied voltage. FERAMs are non-volatile memory devices, because the polarization state of a ferroelectric cell capacitor remains when power is removed from the device. Ferroelectric memories provide certain performance advantages over other forms of non-volatile data storage devices, such as Flash and EEPROM type memories. For example, ferroelectric memories offer short programming (e.g., write access) times and low power consumption. However, access times in SRAM and DRAM type memories are significantly shorter than in FERAM devices.
Hybrid memory devices have been developed, which include volatile and non-volatile portions. For example, memory cells have been constructed combining an SRAM cell or latch with ferroelectric capacitors for non-volatile data storage, which are sometimes referred to as ferroelectric latches or FE latches. An FE latch may be operated as an SRAM, with the capability to backup or save the volatile SRAM data to ferroelectric capacitors. In one mode of operation, the latched data is stored to the ferroelectric capacitors each time the data is written. Alternatively, the cell may be operated as an SRAM cell, with the data being stored to the ferroelectric capacitors only in certain conditions, for example, prior to removing power from the device. Upon powerup, the non-volatile data may be retrieved or restored from the ferroelectric capacitors and transferred to the SRAM cell latch.
FIG. 1 illustrates a conventional FE latch 2 consisting of a CMOS SRAM latch or cell 4 with two internal nodes NODE1 and NODE2, and a non-volatile (e.g., shadow) portion consisting of two ferroelectric capacitors C1 and C2 coupled with NODE1 and NODE2, respectively. The SRAM cell 4 includes two PMOS transistors T1 and T3 and two NMOS transistors T2 and T4 forming a pair of cross-coupled CMOS inverters. The internal nodes NODE1 and NODE2 are cross-coupled to the inverters, with NODE1 being coupled with the gates of transistors T3 and T4, and NODE2 being coupled with the gates of transistors T1 and T2. In addition, transistors T5 and T6 are provided to selectively couple NODE1 and NODE2 to complementary bitlines BL and BLB, respectively, wherein the gates of the access transistors T5 and T6 are coupled to a wordline WL. The nodes NODE1 and NODE2 are further coupled with the upper terminals of the ferroelectric capacitors C1 and C2, respectively, for non-volatile data storage therein, wherein the lower ferroelectric capacitor terminals are coupled to a plateline signal PL.
In operation, the plateline signal PL is generally held low (e.g., at ground or Vss), whereby the volatile SRAM latch 4 operates as a normal SRAM cell, with data being accessed along the bitlines BL and BLB for read or write operations via the transistors T5 and T6, respectively, according to the wordline signal WL. To store the SRAM data to the ferroelectric capacitors C1 and C2, a plateline pulse signal is applied by decoder control circuitry (not shown), by which the capacitors C1 and C2 are polarized to opposite states. In one example, where the SRAM data is such that NODE1 is low (Vss) and NODE2 is high (Vdd), the ferroelectric capacitor C2 is polarized in a first direction or polarization state since the plateline signal PL is initially low. The plateline signal PL is then pulsed high to polarize the other ferroelectric capacitor C1 to a second opposite polarization state or direction, after which the plateline goes low again. In this manner, the high node NODE2 of the SRAM cell 4 corresponds to C2 being programmed to the “high” polarization state, and the low level at NODE1 has been written as a “low” polarization state to C1. Similar operation is found where the data in the SRAM is of an opposite binary value, such as where NODE2 is at a low voltage level (Vss) and NODE1 is at a high voltage level (Vdd).
If power is thereafter removed, and is then re-established, the differences in capacitance at the internal nodes due to the opposite polarization states of C1 and C2 allow the SRAM latch 4 to be restored to its previous data state when the supply voltage Vdd returns to the normal operational level. To read the non-volatile data into the SRAM 4 upon return of the supply voltage Vdd, the plateline PL is held low with the wordline WL deactivated (e.g., low). In one mode of operation, the capacitance difference between the oppositely polarized ferroelectric capacitors C1 and C2 causes T2 and T3 to turn on before T1 and T4 can turn on, whereby NODE1 is pulled low by T2 and NODE2 is pulled high by T3, thereby restoring the data state to the SRAM latch 4. In another possible restore operation, the plateline signal PL is brought high and then low (e.g., pulsed) to provide voltages across the ferroelectric capacitors C1 and C2 such that the ferroelectric capacitor having a “high” polarization state will experience a polarization reversal, with the resulting transferred charge causing the corresponding internal node to rise faster than the other internal node, whereby the non-volatile data state is latched in the SRAM latch 4.
The reliability of the restore operation in the FE latch 2 is only ensured if the threshold voltage Vt of the two inverters (T1, T2 and T3, T4) are well matched. If they are not, the latch 4 can return into an incorrect data state. Accordingly, there is a need for improved FE latch memory devices combining SRAM or other volatile memory cells with non-volatile ferroelectric capacitors for storing data in a semiconductor device.